`include "PRV564Config.v"
`include "PRV564Define.v"
// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or YSYX210152_Simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit YSYX210152_User's needs .Comments are provided in each section to help the YSYX210152_User    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "07/12/2021 17:16:47"
                                                                                
// Verilog Test Bench template for design : ATU
// 
// YSYX210152_Simulation tool : ModelSim (Verilog)
// 

`timescale 1 ps/ 1 ps
module IFU_SimTop();

	reg 			Kernel_CLKi， Kernel_ARSTi;
	reg 			Global_Flush, Global_fence, Global_fencei, Global_fencevma;
	reg 			Branch_Flush;
	reg [`XLEN-1:0] Global_newPC, Branch_newPC;

//-----------------To ID signal----------------------
	wire 			PIP_IDUi_MSC_valid, PIP_IDUi_MSC_InstPageFlt, PIP_IDUi_MSC_InstAccFlt, PIP_IDUi_MSC_InstAddrMis;
	wire [31:0]		PIP_IDUi_DATA_instr;
	wire [`XLEN-1:0]PIP_IDUi_INFO_pc, PIP_IFo_INFO_predictedPC;
	wire [1:0]		PIP_IDUi_INFO_priv;
	reg             PIP_IDUo_FC_ready;

InstrFront #(.ITLB_FIBID(8'hFF)) InstrFront(
    .IFi_CLK                      (Kernel_CLKi),
    .IFi_ARST                     (Kernel_ARSTi),
    .IFi_GFlush                   (Global_Flush),
    .IFi_GPC                      (Global_newPC),
    .IFi_BFlush                   (Branch_Flush),
    .IFi_BPC                      (Branch_newPC),
    .IFi_fencei                   (Global_fencei),
    .IFi_fencevma                 (Global_fencevma),
    //--------------CSR value in----------------
    .CSR_satpppn                  (44'h5aaf),
    .CSR_satpmode                 (`Sv39_Bare),
    .CSR_priv                     (`Machine),
    .CSR_mxr                      (1'b0),
    .CSR_sum                      (1'b0),
    //-----------To next stage-------------------
    .PIP_IFo_MSC_valid            (PIP_IDUi_MSC_valid),
    .PIP_IFo_DATA_instr           (PIP_IDUi_DATA_instr),
    .PIP_IFo_INFO_pc              (PIP_IDUi_INFO_pc),
    .PIP_IFo_INFO_priv            (PIP_IDUi_INFO_priv),
    .PIP_IFo_MSC_InstPageFlt      (PIP_IDUi_MSC_InstPageFlt),
    .PIP_IFo_MSC_InstAccFle       (PIP_IDUi_MSC_InstAccFlt),
    .PIP_IFo_MSC_InstAddrMis      (PIP_IDUi_MSC_InstAddrMis),
    .PIP_IFi_FC_ready             (PIP_IFi_FC_ready),
    //-----------------ITLB_FIB--------------------------
    .ITLB_FIBo_WREN                (ITLB_FIBo_WREN),
    .ITLB_FIBo_REQ                 (ITLB_FIBo_REQ),
    .ITLB_FIBi_ACK                 (ITLB_FIBi_ACK),
    .ITLB_FIBi_FULL                (ITLB_FIBi_FULL),
    .ITLB_FIBo_ID                  (ITLB_FIBo_ID),
    .ITLB_FIBo_CMD                 (ITLB_FIBo_CMD),
    .ITLB_FIBo_BURST               (ITLB_FIBo_BURST),
    .ITLB_FIBo_SIZE                (ITLB_FIBo_SIZE),
    .ITLB_FIBo_ADDR                (ITLB_FIBo_ADDR),
    .ITLB_FIBo_DATA                (ITLB_FIBo_DATA),
    .ITLB_FIBi_ID                  (ITLB_FIBi_ID),
    .ITLB_FIBi_RPL                 (ITLB_FIBi_RPL),
    .ITLB_FIBi_V                   (ITLB_FIBi_V),
    .ITLB_FIBi_DATA                (ITLB_FIBi_DATA),
    //--------------------ICache Interface---------------------------
    .IFo_AQ_V                      (ICache_AQ_V),
    .IFo_AQ_ID                     (ICache_AQ_ID),
    .IFo_AQ_CMD                    (ICache_AQ_CMD),
    .IFo_AQ_CI                     (ICache_AQ_CI),
    .IFo_AQ_WT                     (ICache_AQ_WT),
    .IFo_AQ_BSEL                   (ICache_AQ_BSEL),
    .IFo_AQ_WDATA                  (),
    .IFo_AQ_ADDR                   (ICache_AQ_ADDR),
    .IFi_AQ_FULL                   (ICache_AQ_FULL),
    .IFi_RQ_V                      (ICache_RQ_V),
    .IFi_RQ_ID                     (ICache_RQ_ID),
    .IFi_RQ_WRERR                  (ICache_RQ_WRERR),
    .IFi_RQ_RDERR                  (ICache_RQ_RDERR),
    .IFi_RQ_RDY                    (ICache_RQ_RDY),
    .IFi_RQ_RDATA                  (ICache_RQ_RDATA),
    .IFo_RQ_ACK                    (ICache_RQ_ACK)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin
	ATUi_CLK = 1'b0;
	ATUi_ARST = 1'b1;			//Reset enable
	PIP_ATUi_MSC_valid = 1'b0;	
	PIP_ATUi_FC_ready  = 1'b0;
	ATUi_CSR_mxr = 1'b0;		//mxr mot enable
	ATUi_CSR_sum = 1'b0;
	ATUi_CSR_satp= 64'h8000000000000000;		//Sv39 Page enable
#100
	ATUi_ARST = 1'b0;                                            
// --> end                                             
$display("Running testbench");                       
end
initial begin
	wait(ATUi_ARST == 1'b0) ;
        
end
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
    #5 ATUi_CLK = ~ATUi_CLK;		//Clock period = 10 units 50/50                                                   
                                         
// --> end                                             
end                                                    
endmodule

